AMD's Threadripper line has been inconsistent; the 5000 series was all Threadripper PRO parts, then last year's 7000 series brought back the non-PRO Threadripper options. But even the entry-level Threadripper CPUs and TRX50 motherboards available today are less affordable than HEDT systems were eg. 15 years ago. The high core counts available in mainstream desktop sockets have shifted the boundary between that segment and HEDT, and as a result there aren't good options to step up to a platform with more IO capability without also stepping up to really high CPU core counts.

The cpu cache won't be mismatched though, since the memory controller can mask this. The performance hit will be due to the memory controller having to do the extra reads for parity.

That will be a tiny mismatch, and I wonder if the performance implication of this won't more or less be equal to the performance difference we already have between buffered and unbuffered memory (more or less the same, simply, now that "extra work", moved from inside the dimm, to the memory controller)

So the burst transfers have the same size as when ECC is disabled.

Without the special cache, the number of memory accesses would double, for data and for the extra ECC bits, which would not be acceptable. With the ECC cache, in many cases the reading and writing of the extra ECC bits can be avoided.

There have been published a few benchmarks for inline ECC. The performance loss depends on the cache hit rates, so it varies a lot from program to program. In some cases the speed is lower by only a couple percent, but for some applications the performance loss can be as high as 20% or 30%.